Efficient RTL Coding Standards: 12 Rules for Synthesizable, Maintainable, Timing-Friendly Design

Clean RTL is not just aesthetics. It directly reduces bugs, shortens verification, and improves implementation predictability.

The 12 rules

1. Use explicit intent constructs (always_ff, always_comb)
2. Separate combinational and sequential logic
3. Reset all architectural state intentionally
4. Never infer latches accidentally
5. Parameterize widths and depths
6. Keep signal ownership single and obvious
7. Constrain state machines with complete transitions
8. Code for timing (pipeline where needed)
9. Treat CDC as architecture, not patchwork
10. Add assertions at interfaces
11. Keep naming consistent and reviewable
12. Document trade-offs near the code

Reference FSM skeleton

typedef enum logic [1:0] {IDLE, BUSY, DONE} state_t;
state_t state, next_state;

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) state <= IDLE;
  else state <= next_state;
end

always_comb begin
  next_state = state;
  unique case (state)
    IDLE: if (start) next_state = BUSY;
    BUSY: if (done)  next_state = DONE;
    DONE: next_state = IDLE;
    default: next_state = IDLE;
  endcase
end

Review checklist before check-in

• [ ] Lint-clean or waivers justified
• [ ] No inferred latches
• [ ] Reset behavior verified
• [ ] Assertions added for key invariants
• [ ] CDC crossings documented and synchronized
• [ ] Parameter bounds and widths validated

Assumptions and confidence labels

• High confidence: these rules reduce common RTL and integration failures
• Medium confidence: reset style preference can vary by ASIC/FPGA and tool flow
• Assumption: team enforces reviews and automated lint in CI

Next actions

1. Apply this checklist to your current top module.
2. Fix one readability issue and one robustness issue today.
3. Add automated lint gate if missing.

Great RTL scales because intent is explicit.