
Lead Verification Architect
Lead Verification Architect with expertise in UVM, formal verification, and coverage-driven verification. M.Tech from IIT Delhi.
A practical guide to UVM architecture, phases, factory usage, config_db patterns, and reusable verification strategy for real projects.
A practical analysis of 2026 VLSI trends including AI-assisted EDA, chiplets, advanced packaging, RISC-V, and verification skill shifts.
A practical RTL style guide with synthesis-safe patterns, reset strategy, FSM templates, CDC basics, and a review checklist used by real teams.