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Premium Student

Rishi

Joined Jan 2026

Bio

"VLSI enthusiast and aspiring Verification Engineer. Currently mastering UVM and SystemVerilog architectures."

rishi@reyatech.com

rishi-chips.dev

Engineering Stack

SystemVerilogUVMVerilog-HDLPythonC++Static Timing Analysis

Learning Progress

SystemVerilog for Design

Completed

100%

UVM Methodology Masterclass

In Progress

75%

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UVM Master

Verified on Jan 15, 2026

Perfect Quiz Streak

Verified on Jan 10, 2026

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